1. Field of the Invention
This invention generally relates to very large scale integrated (VLSI) circuit designs. More specifically, the invention relates to leakage reduction in digital CMOS VLSI designs.
2. Background Art
Leakage power (both gate and sub-threshold) is predicted to be the limiting factor in the design of future VLSI systems. MTCMOS (or VDD-gating) is a very popular technique for controlling standby leakage. It adds a high-VTH PFET header or a high-VTH NFET footer device in series to a circuit to reduce leakage in standby mode. Various other incarnations of MTCMOS have been proposed. The main consideration in the implementation of the MTCMOS scheme is the trade-off between standby leakage power and active mode performance.
In general, a PFET device is slower than an NFET device because of the lower mobility of holes compared with electrons. So, a circuit with a high-VTH PFET header is slower than a circuit with a high-VTH NFET footer. However, the PFET header is more effective in reducing gate leakage when the circuit is in standby mode. Thick-oxide high-VTH NFET footer (BGMOS scheme) has been described to control both standby gate and sub-threshold leakages. For silicon-on insulator (SOI) technology, header/footer body biasing schemes have been proposed to boost active-mode MTCMOS performance. It has also been shown that a supplementary capacitor in parallel with the header/footer in MTCMOS circuits is effective for reducing virtual VDD/GND bounce caused by sudden and large current spikes.
It has also been shown that hole mobility is more than doubled on (110) silicon substrates compared with conventional substrates. To fully utilize this fact, a technology, referred to as Hybrid Orientation Technology (HOT), is being used to extend circuit performance. Two HOT structures are possible: HOT-A with PFET on (110) SOI and NFET on (100) silicon epitaxial layer, and HOT-B with NFET on (100) SOI and PFET on (110) silicon epitaxial layer.